The present invention relates to semiconductor devices and methods of making such devices. More particularly, the invention relates to a method of forming multilevel subtractive metallization structures.
The integration of a large number of components on a single integrated circuit (IC) chip requires complex interconnects. Ideally, the interconnect structures should be fabricated with minimal signal delay and optimal packing density. The reliability and performance of integrated circuits may be affected by the qualities of their interconnect structures.
Advanced multiple metallization layers have been used to accommodate higher packing densities as devices shrink below sub-0.25 micron design rules. One such metallization scheme is a dual damascene structure formed by a dual damascene process, which is an additive metallization process. Another metallization scheme is a multilevel subtractive structure formed by a subtractive metallization process. While the additive metallization involves the addition of metal into defined channels in a dielectric material, such as silicon dioxide, the subtractive metallization involves the removal of unprotected portions of a previously deposited metal, for example aluminum, to define portions of integrated circuitry on a substrate.
As illustrated in FIG. 1, one of the known subtractive metallization processes begins with the deposition of a first insulating layer 14 over regions of interconnect metal 12 previously patterned and formed over a semiconductor substrate 10. The insulating layer 14 is patterned by photolithography using a resist layer 16 and a hard mask layer 15 to form via holes 17 (FIGS. 2-3) corresponding to a metal line of the first level interconnect. To prevent the via etch from attacking the underlying substrate, the metal lines are widened at the position of the via, therefore reducing the density of wiring which is obtainable on a given level.
After the via etching is complete, a blanket metal layer is deposited. If a barrier material is required, a blanket layer of the barrier material is deposited prior to the deposition of the metal layer. For example, a titanium or zirconium layer of about few hundred Angstroms thick may be deposited prior to the deposition of a thick aluminum 0.5% copper alloy metallurgy, of about 5,000 to 10,000 Angstroms. Following the metal deposition, a layer of photoresist is deposited and, using an appropriate mask, the metal pattern is imaged into the resist. Then, using an appropriate etching process such as a reactive ion etching, for example, the metal pattern is defined. If a third level of metal is desired, a second layer of the insulator is deposited through which vias are etched, followed by the deposition and etching of another metal level. This process is repeated to acquire the desired number of metal levels.
Subtractive metallization processes such as the one described above pose some drawbacks. One drawback is the substantial undercutting which occurs typically during etching for the formation of vias, such as vias 18 of FIG. 4. Misalignment of vias 18 with the underlying interconnect metal 12 often occurs so that, during etching, the underlying substrate is unfortunately etched also as a result of the vias overlap with the interconnect metal. Accordingly, regions of interconnect metal 12 are patterned wider and larger to eliminate any overlap. However, increasing the width, thickness and/or spacing of the interconnect metal is not compatible with the stringent requirements of packing density. Further, high-resolution devices cannot be effectively produced with these limitations.
The problem could be eliminated by the use of one or more etch stop layers. Although the advantages of using the etch stop layers are significant, the process is complex since separate depositions are required for the etch stop layers. In addition, the most commonly used etch stop material, silicon nitride (Si3N4), has a rather high dielectric constant (k) (approximately 7), which does not satisfy anymore the requirement of resistance-capacitance delay regarding the parasitic capacitance generated by an intermetal insulating layer. As integrated circuits become denser, it is increasingly important to minimize stray capacitance between the metal layers. This is accomplished by using intermetal insulating layers that have a low dielectric constant, such as, for example, organic dielectric materials. Silicon nitride does not satisfy the requirement of small stray capacitance of advanced metallization structures.
Accordingly, there is a need for an improved subtractive metallization structure which reduces production costs and increases productivity. There is also a need for a subtractive metallization process that has zero overlap between the vias and the underlying metal and which does not require etch stop layers. There is further needed a method for decreasing the stray capacitance between the metal layers of subtractive metallization structures.
The present invention provides a method for fabricating a subtractive metallization structure in a semiconductor device. According to one aspect of the invention, productivity can be increased, as the wiring density is increased and fewer processing steps are required. According to another aspect of the invention, the use of high dielectric etch stop materials may be avoided, so as to reduce or minimize stray capacitance.
In an exemplary embodiment, a plurality of low dielectric constant materials are selected so that they have similar methods of formation, as well as similar capacities to withstand physical and thermal stress. The low dielectric constant materials act as insulating layers through which vias are subsequently formed according to subtractive metallization processing. The low dielectric constant materials are selected so that the etchant used for each one has only a small etch rate relative to the other low dielectric constant materials. As a result, the plurality of low dielectric constant materials can act as etch stops relative to other low dielectric constant materials during the fabrication of subtractive metallization structures.
Additional features and advantages of the present invention will be more clearly apparent from the detailed description which is provided in connection with accompanying drawings which illustrate exemplary embodiments of the invention.